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CS5531/32/33/34
16-Bit and 24-Bit ADCs with Ultra Low Noise PGIA
Features
l Chopper
General Description
The CS5531/32/33/34 are highly integrated Analogto-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. To accommodate these applications, the ADCs come as either two-channel (CS5531/32) or four-channel (CS5533/34) devices and include a very low noise chopper-stabilized instrumentation amplifier (6 nV/Hz @ 0.1 Hz) with selectable gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x. These ADCs also include a fourth order modulator followed by a digital filter which provides ten selectable output word rates of 7.5 Hz, 15 Hz, 30 Hz, 60 Hz, 120 Hz, 240 Hz, 480 Hz, 960 Hz, 1.92 kHz, and 3.84 kHz (MCLK = 4.9152 MHz). To ease communication between the ADCs and a microcontroller, the converters include a simple three-wire serial interface which is SPI and Microwire compatible with a Schmitt Trigger input on the serial clock (SCLK). High dynamic range, programmable output rates, and flexible power supply options makes these ADCs ideal solutions for weigh scale and process control applications. ORDERING INFORMATION See page 43
Stabilized PGIA (Programmable Gain Instrumentation Amplifier, 1x to 64x)
-- 6 nV/Hz @ 0.1 Hz (No 1/f noise) -- 500 pA Input Current with Gains >1
l Delta-Sigma
Analog-to-Digital Converter
-- Linearity Error: 0.0007% FS -- Noise Free Resolution: Up to 23 bits
l Two l Scalable
or Four Channel Differential MUX Input Span via Calibration
-- 5 mV to 5 V
l Scalable
VREF Input: Up to Analog Supply l On-chip Guard Drive Output Buffer l Simple three-wire serial interface
-- SPI(R)and MicrowireTM Compatible -- Schmitt Trigger on Serial Clock (SCLK)
l R/W
Calibration Registers Per Channel l Selectable Word Rates: 7.5 Hz to 3,840 Hz l Power Supply Configurations
-- VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V -- VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V -- VA+ = +3 V; VA- = -3 V; VD+ = +3 V
VA+
C1
C2
VREF+
VREF-
VD+
AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4MUX
PGIA 1,2,4,8,16 32,64
DIFFERENTIAL 4TH ORDER MODULATOR
CS PROGRAMMABLE SINC FIR FILTER SERIAL INTERFACE SDI SDO SCLK
(CS5533/34 SHOWN)
CLOCK GENERATOR CALIBRATION SRAM/CONTROL LOGIC
LATCH
VA-
A0/GUARD
A1
OSC1
OSC2
DGND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
OCT `99 DS289PP3 1
CS5531/32/33/34
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................4 ANALOG CHARACTERISTICS..........................................................................4 TYPICAL RMS NOISE (NV), CS5531/32/33/34-AS ...........................................6 TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS .........................6 TYPICAL RMS NOISE (NV), CS5532/34-BS .....................................................7 TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS .........................7 5 V DIGITAL CHARACTERISTICS ....................................................................8 3 V DIGITAL CHARACTERISTICS ....................................................................8 DYNAMIC CHARACTERISTICS ........................................................................8 ABSOLUTE MAXIMUM RATINGS .....................................................................9 SWITCHING CHARACTERISTICS ..................................................................10 2. GENERAL DESCRIPTION .......................................................................................12 2.1. Analog Input ....................................................................................................12 2.1.1. Analog Input Span .................................................................................... 13 2.1.2. Multiplexed Settling Limitations ............................................................13 2.1.3. Voltage Noise Density Performance .....................................................13 2.1.4. No Offset DAC ......................................................................................13 2.2. Overview of ADC Register Structure and Operating Modes ............................14 2.2.1. System Initialization ..............................................................................15 2.2.2. Command Register Quick Reference ..................................................16 2.2.3. Command Register Descriptions ..........................................................17 2.2.4. Serial Port Interface ..............................................................................21 2.2.5. Reading/Writing On-Chip Registers ......................................................22 2.2.6. Setting up the CSRs for a Measurement ..............................................22 2.2.7. Channel-Setup Register Descriptions ..................................................23 2.3. Configuration Register .....................................................................................25 2.3.1. Power Consumption .............................................................................25 2.3.2. Reset System .......................................................................................25 2.3.3. Input Short ............................................................................................25 2.3.4. Guard Signal .........................................................................................26 2.3.5. Voltage Reference Select .....................................................................26 2.3.6. Output Latch Pins .................................................................................27 2.3.7. Configuration Register Descriptions .....................................................28 2.4. Calibration ........................................................................................................29 2.4.1. Calibration Registers ............................................................................29 2.4.2. Gain Register .......................................................................................30 2.4.3. Offset Register .....................................................................................30 2.4.4. Performing Calibrations ........................................................................31
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
SPI is a registered trademark of International Business Machines Corporation. Microwire is a trademark of National Semiconductor Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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2.4.5. Self Calibration ..................................................................................... 31 2.4.6. System Calibration ............................................................................... 32 2.4.7. Calibration Tips .................................................................................... 32 2.4.8. Limitations in Calibration Range ........................................................... 33 2.5. Performing Conversions ..................................................................................33 2.5.1. Single Conversion Mode (MC = 0) ....................................................... 33 2.5.2. Multiple Conversions Mode (MC = 1) ................................................... 33 2.5.3. Examples of Using CSRs to Perform Conversions and Calibrations ... 34 2.6. Conversion Output Coding .............................................................................. 35 2.6.1. Conversion Data Register Descriptions ............................................... 35 2.6.2. Output Coding ...................................................................................... 36 2.7. Digital Filter ..................................................................................................... 36 2.8. Clock Generator .............................................................................................. 37 2.9. Power Supply Arrangements ........................................................................... 37 2.10. Getting Started ................................................................................................ 40 2.11. PCB Layout ..................................................................................................... 40 PIN DESCRIPTIONS ...............................................................................................41 Clock Generator .............................................................................................. 41 Control Pins and Serial Data I/O ..................................................................... 41 Measurement and Reference Inputs ............................................................... 42 Power Supply Connections ............................................................................. 42 SPECIFICATION DEFINITIONS ............................................................................... 43 ORDERING GUIDE .................................................................................................. 43 PACKAGE DRAWINGS ........................................................................................... 44
3.
4. 5. 6.
LIST OF FIGURES
Figure 1. SDI Write Timing (Not to Scale)............................................................................... 11 Figure 2. SDO Read Timing (Not to Scale).............................................................................11 Figure 3. Multiplexer Configuration. ........................................................................................ 12 Figure 4. Input models for AIN+ and AIN- pins. ...................................................................... 13 Figure 5. Measured Voltage Noise Density.............................................................................13 Figure 6. CS5531/32/33/34 Register Diagram. ....................................................................... 14 Figure 7. Command and Data Word Timing. .......................................................................... 21 Figure 8. Guard Signal Shielding Scheme. ............................................................................. 26 Figure 9. Input Reference Model when VRS = 1. ................................................................... 26 Figure 10. Input Reference Model when VRS = 0. ................................................................. 26 Figure 11. Self Calibration of Offset. ....................................................................................... 31 Figure 12. Self Calibration of Gain. .........................................................................................31 Figure 13. System Calibration of Offset. ................................................................................. 32 Figure 14. System Calibration of Gain. ................................................................................... 32 Figure 15. Digital Filter Response (Word Rate = 60 Hz).........................................................36 Figure 16. CS5532 Configured with a Single +5 V Supply. .................................................... 38 Figure 17. CS5532 Configured with 2.5 V Analog Supplies.................................................. 38 Figure 18. CS5532 Configured with 3 V Analog Supplies..................................................... 39 Figure 19. Bridge with Series Resistors. ................................................................................. 39
LIST OF TABLES
Table 1. Command Byte Pointer Table. ..................................................................................34 Table 2. Output Coding for 16-bit CS5531/33 and 24-bit CS5532/34..................................... 36 Table 3. Filter Notch Attenuation............................................................................................. 36
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1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(TA = 25 C; VA+, VD+ = 5 V 5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Hz; Bipolar Mode; Gain = 32; (See Notes 1 and 2.) CS5531-AS/CS5533-AS Parameter Min 16 Typ 0.0015 1 2 TBD DRIFT TBD 8 16 1 TBD Max 0.003 2 4 31 62 3 Unit %FS Bits LSB16 LSB16 nV/C nV/C ppm ppm ppm ppm/C ppm
Accuracy Linearity Error No Missing Codes Bipolar Offset
Unipolar Offset Gain = 1 Gain = 2, 4, 8, 16, 32, 64 Offset Drift /1000 Hours. Bipolar Full Scale Error Unipolar Full Scale Error Full Scale Drift Full Scale Drift /1000 Hours. Offset Drift
(Note 3) (Note 3) (Notes 3 and 4)
(Note 4)
CS5532-AS/CS5534-AS Parameter Min 24 Typ 0.0015 16 32 TBD DRIFT TBD 8 16 1 TBD Max 0.003 32 64 31 62 3 -
CS5532-BS/CS5534-BS Min 24 Typ Max Unit %FS Bits LSB24 LSB24 nV/C nV/C ppm ppm ppm ppm/C ppm
Accuracy Linearity Error No Missing Codes Bipolar Offset
Unipolar Offset Offset Drift
(Note 3) (Note 3)
0.0007 0.0015 16 32 32 TBD DRIFT TBD 8 16 1 TBD 64 31 62 3 -
Gain = 1 (Notes 3 and 4) Gain = 2, 4, 8, 16, 32, 64 Offset Drift /1000 Hours. Bipolar Full Scale Error Unipolar Full Scale Error Full Scale Drift (Note 4) Full Scale Drift /1000 Hours.
Notes: 1. Applies after system calibration at any temperature within -40 C ~ +85 C. 2. Specifications guaranteed by design, characterization, and/or test. LSB is 16 bits for the CS5531/33 and LSB is 24 bits for the CS5532/34. 3. The offset drift is dictated by the gain setting. The offset drift, DRIFT, is (TBD nV/C)/G, where G is the gain of the amplifier. Further note, the specification applies to the device only and does not include any effects by external parasitic thermocouples.
4. Drift over specified temperature range after calibration at power-up at 25 C.
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ANALOG CHARACTERISTICS
(Continued) (See Notes 1 and 2.) Typ Max Unit
Parameter Min Analog Input Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode Gain = 1 VAGain = 2, 4, 8, 16, 32, 64 VA- + 0.7 CVF Current on AIN+ or AINGain = 1 (Note 5) Gain = 2, 4, 8, 16, 32, 64 Input Current Drift Input Leakage for Mux when Off Open Circuit Detect Current 100 Common Mode Rejection dc 50, 60 Hz Input Capacitance Guard Drive Output Voltage Reference Input Range (VREF+) - (VREF-) 1 CVF Current Common Mode Rejection (Note 5) dc 50, 60 Hz Input Capacitance System Calibration Specifications Full Scale Calibration Range Bipolar/Unipolar Mode Offset Calibration Range Bipolar/Unipolar Mode 11 CS5531/32/33/34-AS Parameter Min IA+ ID+ (Note 6) Typ TBD TBD TBD TBD TBD 120 120 Max TBD TBD 30 -
100 500 TBD TBD 300 120 120 60 TBD 2.5 100 120 120 TBD TBD
VA+ V VA+ - 1.7 V nA pA pA/C pA nA dB dB pF A (VA+)(VA-) 22 V nA dB dB pF %FS %FS
CS5532/34-BS Min Typ TBD TBD TBD TBD TBD 120 120 Max 6.5 1.5 40 Unit mA mA mW mW W dB dB
Power Supplies
DC Power Supply Currents (Normal Mode) Power Consumption Normal Mode Standby Sleep dc Positive Supplies dc Negative Supply
Power Supply Rejection
Notes: 5. See the section of the data sheet which discusses input models. 6. All outputs unloaded. All input CMOS levels.
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CS5531/32/33/34
TYPICAL RMS NOISE (nV), CS5531/32/33/34-AS (See notes 7 and 8)
Output Word -3 dB Filter Rate (Hz) Frequency (Hz) 7.5 1.94 15 3.88 30 7.75 60 15.5 120 31 240 62 480 122 960 230 1,920 390 3,840 780 x64 17 24 34 48 68 115 163 229 344 1390 x32 17 25 35 49 70 160 230 321 523 2710 Instrumentation Amplifier Gain x16 x8 x4 19 26 42 27 36 59 39 51 84 54 72 118 77 102 167 276 527 1040 392 748 1480 554 1060 2090 946 1840 3650 5390 10800 21500 x2 79 111 157 222 314 2070 2950 4170 7290 43000 x1 155 218 308 436 616 4150 5890 8340 14600 86100
Notes: 7. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 8. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.
TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS (See Note 9)
Output Word -3 dB Filter Rate (Hz) Frequency (Hz) 7.5 1.94 15 3.88 30 7.75 60 15.5 120 31 240 62 480 122 960 230 1,920 390 3,840 780 9. x64 19 19 18 18 17 16 16 15 15 13 x32 20 20 19 19 18 17 17 16 15 13 Instrumentation Amplifier Gain x16 x8 x4 21 22 22 21 21 21 20 21 21 20 20 20 19 20 20 17 17 17 17 17 17 16 16 16 15 15 15 13 13 13 x2 22 22 21 21 20 17 17 16 15 13 x1 22 22 21 21 20 17 17 16 15 13
Noise Free Resolution is LOG((2xInput Span)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. The input span is calculated in the analog input span section of the data sheet.
Specifications are subject to change without notice.
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TYPICAL RMS NOISE (nV), CS5532/34-BS (See notes 10 and 11)
Output Word -3 dB Filter Rate (Hz) Frequency (Hz) 7.5 1.94 15 3.88 30 7.75 60 15.5 120 31 240 62 480 122 960 230 1,920 390 3,840 780 x64 8.5 12 17 24 34 80 113 159 260 1360 x32 9 13 18 25 36 136 194 274 470 2690 Instrumentation Amplifier Gain x16 x8 x4 10 15 26 15 21 37 21 30 52 29 42 73 42 59 103 260 514 1020 369 730 1450 523 1030 2060 912 1810 3620 5380 10800 21500 x2 50 70 99 140 198 2050 2900 4110 7230 43000 x1 99 139 196 277 392 4090 5810 8230 14500 86000
Notes: 10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 11. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.
TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS (See Notes 12 and 13)
Output Word -3 dB Filter Rate (Hz) Frequency (Hz) 7.5 1.94 15 3.88 30 7.75 60 15.5 120 31 240 62 480 122 960 230 1,920 390 3,840 780 12. x64 20 20 19 19 18 17 17 16 16 13 x32 21 21 20 20 19 17 17 16 16 13 Instrumentation Amplifier Gain x16 x8 x4 22 23 23 22 22 22 21 22 22 21 21 21 20 21 21 18 18 18 17 17 17 17 17 17 16 16 16 13 13 13 x2 23 22 22 21 21 18 17 17 16 13 x1 23 22 22 21 21 18 17 17 16 13
Noise Free Resolution is LOG((2xInput Span)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. The input span is calculated in the analog input span section of the data sheet.
13. Note that the -B devices provide the best noise specifications.
Specifications are subject to change without notice.
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5 V DIGITAL CHARACTERISTICS (TA = 25 C; VA+, VD+ = 5 V 5%; VA-, DGND = 0 V;
See Notes 2 and 14.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Iout = -5.0 mA Iout = 5.0 mA Symbol VIH VIL VOH VOL Iin IOZ Cout Min 0.6 VD+ 0.0 (VD+) - 1.0 Typ 1 9 Max VD+ 0.8 0.4 10 10 Unit V V V V A A pF
3 V DIGITAL CHARACTERISTICS (TA = 25 C; VA+ = 5V 5%; VD+ = 3.0V10%; VA-, DGND =
0V; See Notes 2 and 14.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance 14. All measurements performed under static conditions. Iout = -5.0 mA Iout = 5.0 mA Symbol VIH VIL VOH VOL Iin IOZ Cout Min 0.6 VD+ 0.0 (VD+) - 1.0 Typ 1 9 Max VD+ 0.8 0.4 10 10 Unit V V V V A A pF
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full Scale Step Input) Single conversion mode (See notes 15, 16, 17) Multiple conversions mode, OWR < 3840 Hz Multiple conversions mode, OWR = 3840 Hz Symbol fs ts ts ts Ratio MCLK/16 1/OWR 3/OWR 5/OWR Unit Hz s s s
15. The ADCs use a Sinc5 filter for the 3840 Hz output word rate (OWR) and a Sinc3 filter for the other OWRs. This implies that the filter's settling time with a full scale step input is dictated by the OWR. 16. The single conversion mode only outputs fully settled output conversions. This implies that the effective throughput in the single conversion mode is reduced by 3 times with an OWR of less than 3840 Hz and it is reduced by 5 times with an OWR of 3840 Hz. 17. The multiple conversions mode outputs every conversion. This implies that the filter's settling time with a full scale step input in the multiple conversions mode is dictated by the OWR.
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ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 18.)
Parameter DC Power Supplies (Notes 19 and 20) Positive Digital Positive Analog Negative Analog (Notes 21 and 22) Symbol VD+ VA+ VAIIN IOUT (Note 23) VREF pins AIN Pins PDN VINR VINA VIND TA Tstg Min -0.3 -0.3 +0.3 -0.3 -0.3 -0.3 -40 -65 Typ Max +6.0 +6.0 -3.75 10 25 500 (VA+) + 0.3 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 18. All voltages with respect to ground. 19. VA+ and VA- must satisfy {(VA+) - (VA-)} +6.6 V. 20. VD+ and VA- must satisfy {(VD+) - (VA-)} +7.5 V. 21. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 22. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 23. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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SWITCHING CHARACTERISTICS (TA = 25 C; VA+ = 2.5 V or 5 V 5%; VA- = -2.5V5% or 0 V;
VD+ = 3.0 V 10% or 5 V 5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF; See Figures 1 and 2.) Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times (Note 25) Any Digital Input Except SCLK SCLK Any Digital Output (Note 25) Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 4.9152MHz (Note 26) trise tfall tost SCLK Pulse Width High Pulse Width Low t1 t2 t3 t4 t5 t6 t7 t8 t9 0 250 250 50 20 1.0 100 2 s s ns ms MHz ns ns 50 1.0 100 s s ns (Note 24) External Clock or Internal Oscillator Symbol MCLK 1 40 4.9152 5 60 MHz % Min Typ Max Unit
Fall Times
Start-up
Oscillator Start-up Time
Serial Port Timing
Serial Clock Frequency Serial Clock
SDI Write Timing
CS Enable to Valid Latch Clock Data Set-up Time prior to SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable 50 50 100 100 150 150 150 ns ns ns ns ns ns ns
SDO Read Timing
CS to Data Valid SCLK Falling to New Data Bit CS Rising to SDO Hi-Z
Notes: 24. Device parameters are specified with a 4.9125 MHz clock. 25. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 26. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
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CS
t3
SDI
MSB
MSB-1
t4 t5 t1
LSB
t6
SCLK
t2
Figure 1. SDI Write Timing (Not to Scale).
CS
t7 t9
SDO
MSB
t8
MSB-1
t2
LSB
SCLK
t1
Figure 2. SDO Read Timing (Not to Scale).
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2. GENERAL DESCRIPTION
The CS5531/32/33/34 are highly integrated Analog-to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. To accommodate these applications, the ADCs come as either two-channel (CS5531/32) or fourchannel (CS5533/34) devices and include a very low noise chopper-stabilized programmable gain instrumentation amplifier (PGIA, 6 nV/Hz @ 0.1 Hz) with selectable gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x. These ADCs also include a fourth order modulator followed by a digital filter which provides ten selectable output word rates of 7.5 Hz, 15 Hz, 30 Hz, 60 Hz, 120 Hz, 240 Hz, 480 Hz, 960 Hz, 1.92 kHz, and 3.84 kHz (MCLK = 4.9152 MHz). To ease communication between the ADCs and a micro-controller, the converters include a simple three-wire serial interface which is SPI and Microwire compatible with a Schmitt Trigger input on the serial clock (SCLK).
2.1. Analog Input
Figure 3 illustrates a block diagram of the CS5531/32/33/34. The front end consists of a multiplexer, a unity gain coarse/fine charge input buffer, and a programmable gain chopper-stabilized instrumentation amplifier. The unity gain buffer is activated any time conversions are performed with a gain of one and the instrumentation amplifier is activated any time conversions are performed with gain settings greater than one. The unity gain buffer is designed to accommodate rail to rail input signals. The common-mode plus signal range for the unity gain buffer amplifier is VA- to VA+. Typical CVF (sampling) current for the unity gain buffer amplifier is about 100 nA (MCLK = 4.9152 MHz, see Figure 4). The instrumentation amplifier is chopper-stabilized and operates with a chop clock frequency of MCLK/128. The CVF (sampling) current into the instrumentation amplifier is less than TBD pA over
VREF+ VREFAIN2+ AIN2AIN1+ AIN1-
CS5531/32 IN+ M U INX
IN+
X1
X1
X1
1000 XGAIN 22 nF 1000
X1
AIN4+ AIN4* * * AIN1+ AIN1-
CS5533/34 M U X
ININ+
Differential C1 PIN 4 th Order C2 PIN Modulator
Sinc Digital Filter
5
Programmable Sinc3 Digital Filter
Serial Port
IN-
GAIN is the gain setting of the PGIA (i.e. 2, 4, 8, 16, 32, 64)
Figure 3. Multiplexer Configuration.
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-40C to +85C (MCLK=4.9152 MHz). The common-mode plus signal range of the instrumentation amplifier is (VA-) + 0.7 V to (VA+) - 1.7 V. Figure 4 illustrates the input models for the amplifiers. The dynamic input current for each of the pins can be determined from the models shown. tation amplifier (i.e. a gain setting other than 1) and using a gain setting of 32, the full scale input range can quickly be set to 2.5/32 or about 78mV. Note that these input ranges assume the calibration registers are set to their default values (i.e. Gain = 1.0 and Offset = 0.0).
2.1.2. Multiplexed Settling Limitations
Gain = 2, 4, 8, 16, 32, 64 AIN Vos 1 mV i n = fVos C f=
C = 2.5 pF
MCLK 128 1 Fine 1 Coarse C = 16 pF
Gain = 1
The settling performance of the CS5531/32/33/34 in multiplexed applications is affected by the single-pole low-pass filter which follows the instrumentation amplifier (see Figure 3). To achieve data sheet settling and linearity specifications, it is recommended that a 22 nF C0G capacitor be used. Capacitors as low as 10 nF can be used with some noise degradation.
2.1.3. Voltage Noise Density Performance
Figure 5 illustrates the voltage noise density versus frequency from 0.01 Hz to 10 Hz of a CS5532-BS. The device was powered with 2.5 V supplies, 120 Hz OWR, the 64x gain range, bipolar mode, and with the input short bits enabled.
AIN Vos 20 mV i n = fVos C f = MCLK 16
Figure 4. Input models for AIN+ and AIN- pins.
100 nV/ Hz Gain = 64 10
Note:
The C=2.5pF and C = 16pF capacitors are for input current modeling only. For physical input capacitance see `Input Capacitance' specification under Analog Characteristics.
1 0.01
0.1
1
10
2.1.1. Analog Input Span
The full scale input signal that the converter can digitize is a function of the gain setting and the reference voltage connected between the VREF+ and VREF- pins. The full scale input span of the converter is ((VREF+) - (VREF-))/(GxA), where G is the gain of the amplifier and A is 2 for VRS = 0, or A is 1 for VRS = 1. After reset, the unity gain buffer is engaged. With a 2.5V reference this would make the full scale input range default to 2.5 V. By activating the instrumenDS289PP3
Frequency (Hz)
Figure 5. Measured Voltage Noise Density.
2.1.4. No Offset DAC
An offset DAC was not included in the CS553x family because the high dynamic range of the converter eliminates the need for one. The offset register can be manipulated by the user to mimic the function of a DAC if desired.
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2.2. Overview of ADC Register Structure and Operating Modes
The CS5531/32/33/34 ADCs have an on-chip controller, which includes a number of user-accessible registers. The registers are used to hold offset and gain calibration results, configure the chip's operating modes, hold conversion instructions, and to store conversion data words. Figure 6 depicts a block diagram of the on-chip controller's internal registers. Each of the converters has 32-bit registers to function as offset and gain calibration registers for each channel. The converters with two channels have two offset and two gain calibration registers, the converters with four channels have four offset and four gain calibration registers. These register hold calibration results. The contents of these registers can be read or written by the user. This allows calibration data to be off-loaded into an external EEPROM. The user can also manipulate the contents of these registers to modify the offset or the gain slope of the converter. The converters include a 32-bit configuration register of which 10 of the bits are used for setting options such as the operating power options, resetting the converter, shorting the analog inputs, and enabling diagnostic test bits like the guard signal. A group of registers, called Channel Setup Registers, are also included in the converters. These registers can be used to hold pre-loaded conversion instructions. Each channel setup register is 32 bits long but holds two 16-bit conversion instructions referred to as Setups. Upon power up, these registers can be initialized by the users' microcontroller with conversion instructions. The user can then instruct the converter to perform single or multiple conversions or calibrations with the converter in the mode defined by the Setup referenced. Using the single conversion mode, an 8-bit command word can be written into the serial port. The
Offset Registers (4 x 32) Offset 1 (1 x 32)
Gain Registers (4 x 32) Gain 1 (1 x 32)
Channel Setup Registers (4 x 32) Setup 1 (1 x 16) Setup 3 (1 x 16) Setup 5 (1 x 16) Setup 7 (1 x 16) Setup 2 (1 x 16) Setup 4 (1 x 16) Setup 6 (1 x 16) Setup 8 (1 x 16)
Conversion Data Register (1 x 32) Data (1 x 32)
Offset 2 (1 x 32)
Gain 2 (1 x 32)
CS5533/34 Only
Offset 3 (1 x 32)
Gain 3 (1 x 32)
Offset 4 (1 x 32)
Gain 4 (1 x 32)
Read Only
Serial Interface
CS SDI SDO SCLK
Configuration Register (1 x 32)
Power Save Select Reset System Input Short Guard Signal Voltage Reference Select Output Latch Output Latch Select
Channel Select Gain Word Rate Unipolar/Bipolar Output Latch Delay Time Open Circuit Detect
Write Only Command Register (1 x 8)
Figure 6. CS5531/32/33/34 Register Diagram.
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command includes pointer bits which `point' to a 16-bit command in one of the Channel Setup Registers which is to be executed. The 16-bit Setups can be programmed to perform a conversion on any of the input channels of the converter. More than one of the 16-bit Setups can be used for the same analog input channel. This allows the user to convert on the same signal with either a different conversion speed, a different gain range, or any of the other options, which are in the channel setup registers. Alternatively, the user can set up the registers to perform different conversion conditions on each of the input channels. The ADCs also include multiple conversions capability. User bits in the configuration register of the ADCs can be configured to continuously convert one 16-bit command Setup, performing a conversion according to the content of each 16-bit Setup. In the multiple conversions mode, the conversion data words are loaded into a the data conversion register. The converter issues a flag on the SDO pin when a conversion cycle is completed so the user can read the conversion register. More details will follow. The following pages document how to initialize the converter, perform offset and gain calibrations, and how to configure the converter for the various conversion modes. Each of the bits of the configuration register and of the Channel Setup Registers is described. A list of examples follows the description section. Also the Command Register Quick Reference can be used to decode all valid commands (the first 8-bits into the serial port).
2.2.1. System Initialization
The CS5531/32/33/34 provide no power-on-reset function. To initialize the ADCs, the user must perform a software reset by resetting the ADC's serial port with the Serial Port Initialization sequence. This sequence resets the serial port to the command mode and is accomplished by transmitting 15 SYNC1 command bytes (0xFF hexadecimal), followed by one SYNC0 command (0xFE hexadecimal). Note that this sequence can be initiated at anytime to reinitialize the serial port. To complete the system initialization sequence, the user must also perform a system reset by setting the Reset System (RS) bit in the configuration register. A system reset can also be initiated at any time by writing a logic 1 to the RS bit in the configuration register. After a system reset cycle is complete, the RS bit is automatically returned to logic 0, and the on-chip registers are initialized to the following states:
Configuration Register: Offset Registers: Gain Registers: Channel Setup Registers: 00000000(H) 00000000(H) 01000000(H) 00000000(H)
After a system initialization or reset, the on-chip controller is initialized into command mode where it waits for a valid command (the first 8-bits transmitted into the serial port are transmitted into the command register). Once a valid command is received and decoded, the byte instructs the converter to either acquire data from or transfer data to an internal register(s), or perform a conversion or a calibration. The Command Register Descriptions section can be used to decode all valid commands.
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2.2.2. Command Register Quick Reference
D7(MSB) 0 D6 ARA D5 CS1 D4 CS0 D3 R/W D2 RSB2 D1 RSB1 D0 RSB0
BIT
D7 D6
NAME
Command Bit, C Access Registers as Arrays, ARA
VALUE FUNCTION
0 1 0 1 Must be logic 0 for these commands. These commands are invalid if this bit is logic 1. Ignore this function. Access the respective registers, offset, gain, or channel-setup, as an array of registers. The particular registers accessed are determined by the RS bits. The registers are accessed MSB first with physical channel 0 accessed first followed by physical channel 1 next and so forth. CS1-CS0 provide the address of one of the two (four for CS5533/34) physical input channels. These bits are also used to access the calibration registers associated with the respective physical input channel. Note that these bits are ignored when reading data register. Write to selected register. Read from selected register. Reserved Offset Register Gain Register Configuration Register Conversion Data Register (Read Only) Channel-Setup Registers Reserved Reserved D4 CSRP1 D3 CSRP0 D2 CC2 D1 CC1 D0 CC0
D5-D4
Channel Select Bits, CS1-CS0
00 01 10 11 0 1 000 001 010 011 100 101 110 111 D5
D3 D2-D0
Read/Write, R/W Register Select Bit, RSB3-RSB0
D7(MSB) 1
D6 MC
CSRP2
BIT
D7 D6 D5-D3
NAME
Command Bit, C Multiple Conversions, MC Channel-Setup Register Pointer Bits, CSRP Conversion/Calibration Bits, CC2-CC0
VALUE FUNCTION
0 1 0 1 000 ... 111 000 001 010 011 100 101 110 111 These commands are invalid if this bit is logic 0. Must be logic 1 for these commands. Perform fully settled single conversions. Perform conversions continuously. These bits are used as pointers to the Channel-Setup registers. Either a single conversion or continuous conversions are performed on the channel setup register pointed to by these bits. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
D2-D0
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2.2.3. Command Register Descriptions
READ/WRITE ALL OFFSET CALIBRATION REGISTERS
D7(MSB) 0 D6 1 D5 0 D4 0 D3 R/W D2 0 D1 0 D0 1
Function:
0 1
These commands are used to access the offset registers as arrays.
Write to selected register. Read from selected register.
R/W (Read/Write)
READ/WRITE ALL GAIN CALIBRATION REGISTERS
D7(MSB) 0 D6 1 D5 0 D4 0 D3 R/W D2 0 D1 1 D0 0
Function:
0 1
These commands are used to access the gain registers as arrays.
Write to selected register. Read from selected register.
R/W (Read/Write)
READ/WRITE ALL CHANNEL-SETUP REGISTERS
D7(MSB) 0 D6 1 D5 0 D4 0 D3 R/W D2 1 D1 0 D0 1
Function:
0 1
These commands are used to access the channel-setup registers as arrays.
Write to selected register. Read from selected register.
R/W (Read/Write)
READ/WRITE INDIVIDUAL OFFSET REGISTER
D7(MSB) 0 D6 0 D5 CS1 D4 CS0 D3 R/W D2 0 D1 0 D0 1
Function:
These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed.
Write to selected register. Read from selected register.
R/W (Read/Write)
0 1
CS[1:0] (Channel Select Bits)
00 01 10 11 Offset Register 1 (All devices) Offset Register 2 (All devices) Offset Register 3 (CS5533/34 only) Offset Register 4 (CS5533/34 only)
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READ/WRITE INDIVIDUAL GAIN REGISTER
D7(MSB) 0 D6 0 D5 CS1 D4 CS0 D3 R/W D2 0 D1 1 D0 0
Function:
These commands are used to access each gain register separately. CS1 - CS0 decode the registers accessed.
Write to selected register. Read from selected register.
R/W (Read/Write)
0 1
CS[1:0] (Channel Select Bits)
00 01 10 11 Gain Register 1 (All devices) Gain Register 2 (All devices) Gain Register 3 (CS5533/34 only) Gain Register 4 (CS5533/34 only)
READ/WRITE INDIVIDUAL CHANNEL-SETUP REGISTER
D7(MSB) 0 D6 0 D5 CS1 D4 CS0 D3 R/W D2 1 D1 0 D0 1
Function:
These commands are used to access each channel-setup register separately. CS1 - CS0 decode the registers accessed.
Write to selected register. Read from selected register.
R/W (Read/Write)
0 1
CS[1:0] (Channel Select Bits)
00 01 10 11 Channel-Setup Register 1 (All devices) Channel-Setup Register 2 (All devices) Channel-Setup Register 3 (All devices) Channel-Setup Register 4 (All devices)
READ/WRITE CONFIGURATION REGISTER
D7(MSB) 0 D6 0 D5 0 D4 0 D3 R/W D2 0 D1 1 D0 1
Function:
0 1
These commands are used to read from or write to the configuration register.
Write to selected register. Read from selected register.
R/W (Read/Write)
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PERFORM CONVERSION
D7(MSB) 1 D6 MC D5 CSRP2 D4 CSRP1 D3 CSRP0 D2 0 D1 0 D0 0
Function:
These commands instruct the ADC to perform either a single conversion or continuous conversions on the physical input channel pointed to by the pointer bits (CSRP2 - CRSP0) in the channel-setup register.
Perform fully settled single conversions. Perform conversions continuously.
MC (Multiple Conversions)
0 1
CSRP [2:0] (Channel Setup Register Pointer Bits)
000 001 010 011 100 101 110 111 Setup 1 (All devices) Setup 2 (All devices) Setup 3 (All devices) Setup 4 (All devices) Setup 5 (All devices) Setup 6 (All devices) Setup 7 (All devices) Setup 8 (All devices)
READ CONVERSION DATA REGISTER
D7(MSB) 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0
Function:
This command is used to read from the conversion data register.
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PERFORM CALIBRATION
D7(MSB) 1 D6 0 D5 CSRP2 D4 CSRP1 D3 CSRP0 D2 CC2 D1 CC1 D0 CC0
Function:
These commands instruct the ADC to perform a calibration on the physical input channel selected by the setup register which is chosen by the command byte pointer bits (CSRP2 CSRP0).
Setup 1 (All devices) Setup 2 (All devices) Setup 3 (All devices) Setup 4 (All devices) Setup 5 (All devices) Setup 6 (All devices) Setup 7 (All devices) Setup 8 (All devices)
CSRP [2:0] (Channel Setup Register Pointer Bits)
000 001 010 011 100 101 110 111
CC [2:0] (Calibration Control Bits)
000 001 010 011 100 101 110 111 Reserved Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
SYNC1
D7(MSB) 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1
Function:
SYNC0
D7(MSB) 1
Part of the serial port re-initialization sequence.
D6 1
D5 1
D4 1
D3 1
D2 1
D1 1
D0 0
Function:
NULL
D7(MSB) 0
End of the serial port re-initialization sequence.
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Function:
This command is used to clear a port flag and keep the converter in the continuous conversion mode.
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2.2.4. Serial Port Interface
The CS5531/32/33/34's serial interface consists of four control lines: CS, SDI, SDO, SCLK. Figure 7 details the command and data word timing. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied low, the port can function as a three wire interface. SDI, Serial Data In, is the data signal used to transfer data to the converters. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1.
CS
SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC's serial port. The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the port logic. To accommodate optoisolators SCLK is designed with a Schmitt-trigger input to allow an optoisolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an optoisolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA.
SCLK
SDI
Command Time 8 SCLKs
MSB
LSB
Data Time 32 SCLKs
Write Cycle
CS
SCLK
SDI
Command Time 8 SCLKs
SDO
MSB
LSB
Data Time 32 SCLKs
Read Cycle
CS
SCLK
SDI Command Time 8 SCLKs SDO
td *
MCLK /OWR Clock Cycles
8 SCLKs Clear SDO Flag Data Conversion Cycle
MSB
LSB
Data Time 32 SCLKs
* td = MCLK/OWR clock cycles for each conversion except the first conversion which will take MCLK/OWR + 7 clock cycles
Figure 7. Command and Data Word Timing.
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2.2.5. Reading/Writing On-Chip Registers
The CS5531/32/33/34's offset, gain, configuration, and channel-setup registers are readable and writable while the conversion data register is read only. As shown in Figure 7, to write to a particular register the user must transmit the appropriate write command and then follow that command by 32 bits of data. For example, to write 0x80000000 (hexadecimal) to physical channel one's gain register, the user would first transmit the command byte 0x02 (hexadecimal) followed by the data 0x80000000 (hexadecimal). Similarly, to read a particular register the user must transmit the appropriate read command and then acquire the 32 bits of data. Once a register is written to or read from, the serial port returns to the command mode. In addition to accessing the internal registers one at a time, the gain and offset registers as well as the channel-setup registers, can be accessed as arrays (i.e. the entire register set can be accessed with one command). For example, to write 0x80000000 (hexadecimal) to all four gain registers, the user would transmit the command 0x42 (hexadecimal) followed by four iterations of 0x80000000 (hexadecimal), (i.e. 0x42 followed by 0x80000000, 0x80000000, 0x80000000, 0x80000000). The registers are written to or read from in sequential order (i.e, 1, followed by 2, then 3, then 4). Once the registers are written to or read from, the serial port returns to the command mode.
2.2.6. Setting up the CSRs for a Measurement
The CS5531/32/33/34 have four Channel-Setup Registers (CSRs). Each CSR contains two 16-bit Setups which are programmed by the user to contain data conversion information such as: 1) which physical channel will be converted, 2) at what gain will the channel be converted, 3) at what word rate will the channel be converted, 4) will the output conversion be unipolar or bipolar, 5) what will be the state of the output latch during the conversion, 6) will the converter delay the start of a conversion to allow time for the output latch to settle before the conversion is begun, and 7) will the open circuit detect current source be activated for that Setup. Note that a particular physical input channel can be represented in more than one Setup with different output rates, gain ranges, etc. (i.e. each Setup is independently defined). Refer to the Channel-Setup Register Descriptions section for more details. Each 32-bit CSR is individually accessible and contains two 16-bit Setups. As an example, to configure Setup 1 in the CS5531/32/33/34 with the write individual channel-setup register command (0x05 hexadecimal), bits 31 to 16 of CSR 1 contains the information for Setup 1 and bits 15 to 0 contain the information for Setup 2. Note that while reading/writing CSRs, two Setups are accessed in pairs as a single 32-bit CSR register. Even if one of the Setups isn't used, it must be written to or read. Examples detailing the power of the CSRs are provided in the Use of Pointers in the Command Byte section.
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2.2.7. Channel-Setup Register Descriptions
CSR #1 Setup 1 Bits <127:112> Setup 2 Bits <111:96>
#4
Setup 7 Bits <31:16> D30 CS0 D14 CS0 D29 G2 D13 G2 D28 G1 D12 G1 D27 G0 D11 G0
Setup 8 Bits <15:0> D26 WR3 D10 WR3 D25 WR2 D9 WR2 D24 WR1 D8 WR1 D23 WR0 D7 WR0 D22 U/B D6 U/B D21 OL1 D5 OL1 D20 OL0 D4 OL0 D19 DT D3 DT D18 OCD D2 OCD D17 NU D1 NU D16 NU D0 NU
D31(MSB) CS1 D15 CS1
CS1-CS0 (Channel Select Bits) [31:30] [15:14]
00 01 10 11 Select physical channel 1 (All devices) Select physical channel 2 (All devices) Select physical channel 3 (CS5533/34 only) Select physical channel 4 (CS5533/34 only)
G2-G0 (Gain Bits) [29:27] [13:11]
000 001 010 011 100 101 110 Gain = 1, (Input Span = [(VREF+)-(VREF-)]/1 for unipolar). Gain = 2, (Input Span = [(VREF+)-(VREF-)]/2 for unipolar). Gain = 4, (Input Span = [(VREF+)-(VREF-)]/4 for unipolar). Gain = 8, (Input Span = [(VREF+)-(VREF-)]/8 for unipolar). Gain = 16, (Input Span = [(VREF+)-(VREF-)]/16 for unipolar). Gain = 32, (Input Span = [(VREF+)-(VREF-)]/32 for unipolar). Gain = 64, (Input Span = [(VREF+)-(VREF-)]/64 for unipolar).
WR3-WR0 (Word Rate) [26:23] [10:7]
Word Rates apply to continuous conversion mode. In single conversion mode, an output will take three conversions to settle. Only the third output will be provided to the serial port. Bit 0000 0001 0010 0011 0100 1000 1001 1010 1011 WR (4.9152 MHz) 120 Hz 60 Hz 30 Hz 15 Hz 7.5 Hz 3840 Hz 1920 Hz 960 Hz 480 Hz WR (4.096 MHz) 100 Hz 50 Hz 25 Hz 12.5 Hz 6.25 Hz 3200 Hz 1600 Hz 800 Hz 400 Hz Clock Cycles (40960 MCLK cycles) (81920 MCLK cycles) (163840 MCLK cycles) (327680 MCLK cycles) (655360 MCLK cycles) (1280 MCLK cycles) (2560 MCLK cycles) (5120 MCLK cycles) (10240 MCLK cycles) (20480 MCLK cycles)
1100 240 Hz 200 Hz All other combinations are not used.
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U/B (Unipolar / Bipolar) [22] [6]
0 1 Select Bipolar mode. Select Unipolar mode.
OL1-OL0 (Output Latch Bits) [21:20] [5:4]
The latch bits will be set to the logic state of these bits upon command word execution when the output latch select bit (OLS) in the configuration register is logic 0. Note that the logic outputs on the chip are powered from VA+ and VA-. 00 01 10 11 A0 = 0, A1 = 0 A0 = 0, A1 = 1 A0 = 1, A1 = 0 A0 = 1, A1 = 1
DT (Delay Time Bit) [19] [3]
When set, the converter will wait for a delay time before starting a conversion. This allows settling time for A0 and A1outputs before a conversion begins. The delay time will be 1280 MCLK cycles. 0 1 Normal mode. Wait 1280 MCLK cycles before starting conversion.
OCD (Open Circuit Detect Bit) [18] [2]
When set, this bit activates a 300 nA current source on the input channel (AIN+) selected by the channel select bits. Note that the 300nA current source is rated at 25C. At -55C, the current source doubles to approximately 600nA. This feature is particularly useful in thermocouple applications when the user wants to drive a suspected open thermocouple lead to a supply rail. 0 1 Normal mode. Activate current source.
NU (Not Used) [17:16] [1:0]
These bits are reserved for future upgrade.
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2.3. Configuration Register
To ease the architectural design, the configuration register is thirty-two bits long, however, only ten of the thirty two bits are used. The following sections detail the bits in the configuration register. the Gain = 1 mode, the PGIA is powered down. In this mode, the power consumed in the normal power mode is reduced to TBD mW. The sleep and standby modes are not affected.
2.3.2. Reset System
The reset system (RS) bit permits the user to perform a system reset. A system reset can be initiated at any time by writing a logic 1 to the RS bit in the configuration register. After a system reset cycle is complete, the reset valid (RV) bit is set indicating that the internal logic was properly reset. The RV bit is cleared after the configuration register is read. Note that the on-chip registers are initialized to the following states.
Configuration Register: Offset Registers: Gain Registers: Channel Setup Registers: 00000000(H) 00000000(H) 01000000(H) 00000000(H)
2.3.1. Power Consumption
The CS5531/32/33/34 accommodate three power consumption modes: normal, standby, and sleep. The normal mode, the default mode, is entered after power is applied. In this mode, the CS5531/32/33/34-AS versions typically consume 30 mW. The CS5532/34-BS versions typically consume 40 mW. The last two modes are referred to as the power save modes. They power down most of the analog portion of the chip and stop filter convolutions. The power save modes are entered whenever the power down (PDW) bit of the configuration register is set to logic 1. The particular power save mode entered depends on state of the PSS (Power Save Select) bit. If PSS is logic 0, the converter enters the standby mode reducing the power consumption to TBD mW. The standby mode leaves the oscillator and the on-chip bias generator for the analog portion of the chip active. This allows the converter to quickly return to the normal mode once PDW is set back to a logic 1. If PSS and PDW are both set to logic 1, the sleep mode is entered reducing the consumed power to around TBD W. Since this sleep mode disables the oscillator, approximately a 20 ms oscillator start-up delay period is required before returning to the normal mode. If an external clock is used no delay is necessary. Further note that when the chips are used in
Further note that after reset the RS bit automatically returns to logic 0 and the ADCs return to the command mode where they wait for a valid command. Also, the RS bit is the only bit in the configuration register that can be set when initiating a reset.
2.3.3. Input Short
The input short bit allows the user to internally ground all the inputs of the multiplexer. This is a useful function because it allows the user to easily test the grounded input performance of the ADC and eliminate the noise effects due to the external system.
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2.3.4. Guard Signal
The guard signal bit is a bit that modifies the function of A0. When set, this bit outputs the common mode voltage of the instrumentation amplifier on A0. This feature is useful when the user wants to connect an external shield to the common mode potential of the instrumentation amplifier to protect against leakage. Figure 8 illustrates a typical connection diagram for the guard signal.
2.3.5. Voltage Reference Select
The voltage reference select (VRS) bit selects the size of the sampling capacitor used to sample the voltage reference. The bit should be set based upon the magnitude of the reference voltage to achieve optimal performance. Figures 9 and 10 model the effects on the reference's input impedance and input current for each VRS setting. As the models show, the reference includes a coarse/fine charge buffer which reduces the dynamic current demand of the external reference. The reference's input buffer is designed to accommodate rail-to-rail (common-mode plus signal) input voltages. The differential voltage between the VREF+ and VREF- can be any voltage from 1.0 V up to the analog supply (depending on how VRS is configured), however, the VREF+ cannot go above VA+ and the VREF- pin can not go below VA-. For a single-ended reference voltage, the reference voltage is input into the VREF+ pin of the converter and the VREF- pin is grounded. Note that if 3 V supplies are used, the supplies must be established before the reference voltage.
CS5531/32/33/34
A0/GUARD
+5 VA +
40 A typical
AIN+ out p
VIN+ Common Mode = 2.5 V VIN AINcenter x1
out m
Figure 8. Guard Signal Shielding Scheme.
1 Fine 2 Coarse C = 22pF
1 Fine 2 Coarse C = 11pF
VREF Vos 15 mV i n = fVos C
VREF Vos 30 mV i n = fVos C f=
f = MCLK 16 VRS = 1; 1 V VREF 2.5 V
MCLK 16 VRS = 0; 2.5 V < VREF VA+
Figure 9. Input Reference Model when VRS = 1.
Figure 10. Input Reference Model when VRS = 0.
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2.3.6. Output Latch Pins
The A1-A0 pins of the ADCs mimic the D21D20/D5-D4 bits of the channel-setup registers if the output latch select bit is logic 0 (default). If the output latch select bit is logic 1 then A1-A0 mimic the output latch bit setting in the configuration register. These two options give the user a choice of allowing the latch outputs to change anytime a different CSR is selected for a conversion; or to allow the latch bits to remain latched to a fixed state (determined by the configuration register bit) for all CSR selections. In either case, A1-A0 can be used to control external multiplexers and other logic functions outside the converter. The A1-A0 outputs can sink or source at least 1 mA, but it is recommended to limit drive currents to less than 20 A to reduce self-heating of the chip. These outputs are powered from VA+ and VA-. Their output voltage will be limited to the VA+ voltage for a logic 1 and VA- for a logic 0.
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2.3.7. Configuration Register Descriptions
D31(MSB) D30 PSS PDW D15 D14 NU NU D29 RS D13 NU D28 RV D12 NU D27 IS D11 NU D26 GB D10 NU D25 VRS D9 NU D24 A1 D8 NU D23 A0 D7 NU D22 OLS D6 NU D21 NU D5 NU D20 NU D4 NU D19 NU D3 NU D18 NU D2 NU D17 NU D1 NU D16 NU D0 NU
PSS (Power Save Select)[31]
0 1 Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive).
PDW (Power Down Mode)[30]
0 1 Normal Mode Activate the power save select mode.
RS (Reset System)[29]
0 1 Normal Operation. Activate a Reset cycle. Bit automatically returns to logic 0 after reset.
RV (Reset Valid)[28]
0 1 Normal Operation System got reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read.
IS (Input Short)[27]
0 1 Normal Input All signal input pairs for each channel are shorted internally.
GB (Guard Signal Bit)[26]
0 1 Normal Operation of A0 as an output latch. A0's output is modified to output the common mode output voltage of the instrumentation amplifier (typically 2.5 V). The output latch select bit is ignored when the guard buffer is activated. 2.5 V < VREF VA+ 1 V VREF 2.5V
VRS (Voltage Reference Select)[25]
0 1
A1-A0 (Output Latch bits)[24:23]
The latch bits (A0 and A1) will be set to the logic state of these bits upon command word execution if the output latch select bit (OLS) is set. Note that these logic outputs are powered from VA+ and VA-. 00 01 10 11 A0 = 0, A1 = 0 A0 = 0, A1 = 1 A0 = 1, A1 = 0 A0 = 1, A1 = 1
Output Latch Select, OLS[22]
0 1 When low, uses the Channel-Setup Register as the source of A1 and A0. When set, uses the Configuration Register as the source of A1 and A0.
NU (Not Used)[21:0]
0 Must always be logic 0. Reserved for future upgrades.
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2.4. Calibration
Calibration is used to set the zero and gain slope of the ADC's transfer function. The CS5531/32/33/34 offer both self calibration and system calibration.
Note: 1) After the ADCs are reset, they are functional and can perform measurements without being calibrated (remember that the VRS bit in the configuration register must be configured). In this case, the converter will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words. Any initial offset and gain errors in the internal circuitry of the chip will remain. 2) Calibrations steps each take one conversion cycle to complete. At the end of the calibration step, SDO falls low to indicate that a calibration is complete. 3) Offset calibration must be performed before gain calibration because the gain slope is referenced from the offset calibrations.
2.4.1. Calibration Registers
The CS5531/32/33/34 converters have an individual offset and gain register for each channel input. The gain and offset registers, which are used during both self and system calibration, are used to set the zero and gain slope of the converter's transfer function. As shown in Offset Register section, one LSB in the offset register is 2-24 proportion of the input span (bipolar span is 2 times the unipolar span). The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). Note that the magnitude of the offset that is trimmed from the input is mapped through the gain register. The converter can typically trim 100 percent of the input span. As shown in the Gain Register section, the gain register spans from 0 to (32 - 2-22). The decimal equivalent meaning of the gain register is
N 4 3 2 -N 4 D = b D28 2 + ( b D27 2 + b D26 2 + ... + b N 2 ) = b D28 2 +
bi 2
i=0
-i
where the binary numbers have a value of either zero or one (bD28 corresponds to bit D28).
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2.4.2. Gain Register
MSB NU 0 D15 2 0
-9
D30 NU 0 D14 2
-10
D29 25 0 D13 2 0
-11
D28 24 0 D12 2
-12
D27 23 0 D11 2
-13
D26 22 0 D10 2
-14
D25 21 0 D9 2
-15
D24 20 1 D8 2
-16
D23 2-1 0 D7 2
-17
D22 2-2 0 D6 2
-18
D21 2-3 0 D5 2
-19
D20 2-4 0 D4 2
-20
D19 2-5 0 D3 2
-21
D18 2-6 0 D2 2 0
22
D17 2-7 0 D1 2
-23
D16 2-8 0 LSB 2-24 0
0
0
0
0
0
0
0
0
0
0
0
0
The gain register span is from 0 to (32-2-24). After Reset D24 is 1, all other bits are `0'.
2.4.3. Offset Register
MSB Sign 0 D15 2-17 0 D30 2 0
-2
D29 2-3 0 D13 2-19 0
D28 2-4 0 D12 2-20 0
D27 2-5 0 D11 2-21 0
D26 2-6 0 D10 2-22 0
D25 2-7 0 D9 2-23 0
D24 2-8 0 D8 2-24 0
D23 2-9 0 D7 NU 0
D22 2-10 0 D6 NU 0
D21 2-11 0 D5 NU 0
D20 2-12 0 D4 NU 0
D19 2-13 0 D3 NU 0
D18 2-14 0 D2 NU 0
D17 2-15 0 D1 NU 0
D16 2-16 0 LSB NU 0
D14 2-18 0
One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span). Offset and data word bits align by MSB. After reset, all bits are `0'.
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2.4.4. Performing Calibrations
To perform a calibration the user must send a command byte with its MSB=1, its pointer bits (CSRP2-CSRP0) set to address the desired Setup to calibrate, and the appropriate calibration bits (CC2CC0) set to choose the type of calibration to be performed. Note that calibration assumes that the CSRs have been previously initialized because the information concerning the physical channel, its filter rate, gain range, and polarity, comes from the channel-setup register being addressed by the pointer bits in the command byte. Once the CSRs are initialized, a calibration can be performed with one command byte. Once a calibration cycle is complete, SDO falls and the results are stored in either the gain or offset register for the physical channel being calibrated. Note that if additional calibrations are performed on the same physical channel referenced by a different Setups with different filter rates, gain ranges, or conversion modes, the last calibration results will replace the effects from the previous calibration as only one offset and gain register is available per physical channel. Further note that only one calibration is performed with each command byte. To calibrate all the channels additional calibration commands are necessary.
2.4.5. Self Calibration
The CS5531/32/33/34 offer both self offset and self gain calibrations. For the self-calibration of offset, the converters internally tie the inputs of the amplifier together and routes them to the AIN- pin as shown in Figure 11. For proper self-calibration of offset to occur, the AIN pins must be at the proper common-mode-voltage as specified in the Analog Characteristics section. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and VREF- as shown in Figure 12. Self-calibration of gain is performed in the GAIN = 1x mode without regard to the setup register's gain setting. Gain errors in the PGIA gain steps 2x to 64x are not calibrated as this would require an accurate low voltage source other than the reference voltage. A system calibration of gain should be performed if accurate gains are to be achieved on the 2x and up ranges.
S1 OPEN AIN+ S2 CLOSED AIN+ XGAIN +
OPEN AIN+ + XGAIN AINVREF+ Reference + - VREFOPEN
CLOSED
+
-
CLOSED
Figure 11. Self Calibration of Offset.
Figure 12. Self Calibration of Gain.
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2.4.6. System Calibration
For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converters. Figure 13 illustrates system offset calibration. As shown in Figure 14, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the System Calibration Specifications). For maximum accuracy, calibrations should be performed for both offset and gain (selected by changing the G2-G0 bits of the channel-setup registers). Note that only one gain range can be calibrated per physical channel. And if factory calibration of the user's system is performed using the system calibration capabilities of the CS5531/32/33/34, the offset and gain register contents can be read by the system microcontroller and recorded in EEPROM. These same calibration words can then be uploaded into the offset and gain registers of the converter when power is first applied to the system, or when the gain range is changed. Note that if a user wants to use uncalibrated conversions, the uncalibrated gain accuracy is 1 percent. Further note that the gain tracking from range to range is not affected by calibration. Gain tracking from range to range is 0.1 percent. Note that the gain from the offset register to the output is approximately 1.8 decimal, not 1. If a user wants to calculate the calibration coefficients externally, they will need to divide the content of the offset register by the scale factor 01D5C315 hexadecimal while in the bipolar mode (for unipolar mode divide by two).
2.4.7. Calibration Tips
Calibration steps are performed at the output word rate selected by the WR2-WR0 bits of the channel setup registers. Since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. Also, to minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port.
External Connections + AIN+ 0V + AINXGAIN CM + -
+
Full Scale + -
External Connections + AIN+ XGAIN AIN+
CM + -
Figure 13. System Calibration of Offset.
Figure 14. System Calibration of Gain.
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2.4.8. Limitations in Calibration Range
System calibration can be limited by signal headroom in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. For gain calibration, the full scale input signal can be reduced to the point in which the gain register reaches its upper limit of (32-2-64 decimal). Under nominal conditions, this occurs with a full scale input signal equal to about 1/32 the nominal full scale. With the converter's intrinsic gain error, this full scale input signal may be higher or lower. In defining the minimum Full Scale Calibration Range (FSCR) under Analog Characteristics, margin is retained to accommodate the intrinsic gain error. Alternatively the input full scale signal can be increased to a point in which the modulator reaches its 1's density limit of 90 percent, which under nominal condition occurs when the full scale input signal is 1.1 times the nominal full scale. With the chip's intrinsic gain error, this input full scale input signal maybe higher or lower. In defining the maximum FSCR, margin is again incorporated to accommodate the intrinsic gain error. to clear the SDO flag. During the first 8 SCLKs, SDI must be logic 0. The last 32 SCLKs are needed to read the conversion result. Note that the user is forced to read the conversion in single conversion mode as SDO will remain low (i.e. the serial port is in data mode) until SCLK transitions 40 times. After reading the data, the serial port returns to the command mode, where it waits for a new command to be issued.
Note: In single conversion mode only fully settled data conversions are output to the data conversion register. Since the converter uses a Sinc5 filter for the 3840 Hz word rate, the effective word rate in the single conversion mode will be 1/5 the normal rate (3840/5 which is 768 Hz, MCLK = 4.9152 MHz). Since the converter uses a Sinc3 filter for all other rates, their effective rates will be cut by 1/3 as three conversion are required to fully settle the Sinc3 filter.
2.5.2. Multiple Conversions Mode (MC = 1)
Based on the information provided in the channelsetup registers (CSRs), continuous conversions are repeatedly performed using the Setup register contents pointed to by the conversion command. The command byte includes a pointer address to the Setup register to be used during the conversion. Once transmitted, the serial port enters data mode where it waits until a conversion is complete. After the conversion is done, SDO falls to logic 0. Forty SCLKs are then needed to read the conversion. The first 8 SCLKs are used to clear the SDO flag. The last 32 SCLKs are needed to read the conversion result. If `00000000' is provided to SDI during the first 8 SCLKs when the SDO flag is cleared, the converter remains in this conversion mode and continues to convert the selected channel using the same CSR Setup. While in this mode, not every conversion word needs to be read. The user needs only to read the conversion words required for the application as SDO rises and falls to indicate the availability of a new conversion. Note that if a conversion is not read it will be lost and replaced by a new conversion. To exit this conversion mode the
33
2.5. Performing Conversions
The CS5531/32/33/34 offers two modes of performing conversions. The three sections that follow detail the differences and provide examples illustrating how to use the conversion modes with the channel-setup registers.
2.5.1. Single Conversion Mode (MC = 0)
Based on the information provided in the channelsetup registers (CSRs), a single conversion is performed after the user transmits the single conversion command. The command byte includes a pointer address to the Setup register to be used during the conversion. Once transmitted, the serial port enters data mode where it waits until a conversion is complete. After the conversion is done, SDO falls to logic 0. Forty SCLKs are then needed to read the conversion. The first 8 SCLKs are used
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user must provide `11111111' to the SDI pin during the first 8 SCLKs. If the user decides to exit, 32 SCLKs are required to clock out the last conversion before the converter will return to the command mode.
Note: If a calibration or a single conversion is performed before a multiple conversions command is given, the user must ignore the first three (for OWRs less than 3840 Hz, MCLK = 4.9152 MHz) or first five (for OWR equal to 3840 Hz) conversions in multiple conversions mode as residual filter coefficients must be flushed from the filter before accurate conversion are performed.
Example 1: single conversion with Setup 1. The command issued is `10000000'. These settings instruct the converter to perform a single conversion with Setup 1's settings as CSRP2 - CSRP0 = `000' (which happens to be physical channel 4 in this example). After the command is received and decoded the ADC performs a conversion on physical channel 4 and then SDO falls to indicate that the conversion is complete. To read the conversion, 40 SCLKs are then required. Once acquired, the serial port returns to the command mode. Example 2: continuous conversion with Setup 3. The command issued is `11010000'. These settings instruct the converter to perform continuous conversions with Setup 3's settings as CSRP2 - CSRP0 = `010' (which happens to be physical channel 1 in this example). After the command is received and decoded the ADC performs a conversion on physical channel 1 and then SDO falls to indicate that the conversion is complete. The user now has three options. The user can acquire the conversion and remain in this mode, acquire the conversion and exit this mode, or ignore the conversion and wait for a new conversion at the next update interval. Example 3: calibration with Setup 4. The command issued is `10011001'. These settings instruct the converter to perform a self offset calibration with Setup 4's settings as CSRP2 - CSRP0 = `011' (which happens to be physical channel 2 in this example). After the command is received and decoded the ADC performs a self offset calibration on physical channel 2 and then SDO falls to indicate that the calibration is complete. To perform additional calibrations, more commands have to be issued.
Note: The CSRs need not be written. If they are not initialized, all the Setups point to their default settings irrespective of the single conversion, multiple single conversion, or calibration mode (i.e conversion can be performed, but only physical channel 1 will be converted). Further note that filter convolutions are reset (i.e. flushed) if consecutive conversions are
2.5.3. Examples of Using CSRs to Perform Conversions and Calibrations
Any time a calibration or conversion command is issued (C, MC, and CC2-CC0 bits must be properly set), the CSRP2-CSRP0 bits in the command byte are used as pointers to address one of the Setups in the channel-setup registers (CSRs). Table 1 details the address decoding of the pointer the bits.
(CSRP2-CSRP0) CSR Location 000 CSR #1 001 010 011 100 101 110 111 Setup 1 2 3 4 5 6 7 8
CSR #1 CSR #2 CSR #2 CSR #3 CSR #3 CSR#4 CSR #4
Table 1. Command Byte Pointer Table.
The examples that follow detail situations that a user might encounter when acquiring a conversion or calibrating the converter. These examples assume that the CSRs are programmed with the following physical channel order: 4, 1, 1, 2, 4, 3, 4, 4. A physical channel is defined as the actual input channel (AIN1 to AIN4) to which an external signal is connected.
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performed on two different physical channels. If consecutive conversions are performed on the same physical channel, the filter is not reset. This allows the ADCs to more quickly settle full scale step inputs.
2.6. Conversion Output Coding
The CS5531/32/33/34 output 16-bit (CS5531/33) and 24-bit (CS5532/34) data conversion words. To read a conversion word the user must read the conversion data register. The conversion data register is 32 bits long and outputs the conversions MSB first. The last byte of the conversion data register 2.6.1. Conversion Data Register Descriptions
CS5531/33 (16-BIT CONVERSIONS)
D31(MSB) D30 MSB 14 D15 D14 0 0 D29 13 D13 0 D28 12 D12 0 D27 11 D11 0 D26 10 D10 0 D25 9 D9 0 D24 8 D8 0
contains data monitoring flags. The channel indicator (CI) bits keep track of which physical channel was converted and the overrange flag (OF) monitors to determine if a valid conversion was performed. Refer to the Conversion Data Register Descriptions section for more details. The CS5531/32/33/34 output data conversions in binary format when operating in unipolar mode and in two's complement when operating in bipolar mode. Refer to the Output Coding section for more details.
D23 7 D7 0
D22 6 D6 0
D21 5 D5 0
D20 4 D4 0
D19 3 D3 0
D18 2 D2 OF
D17 1 D1 CI1
D16 LSB D0 CI0
CS5532/34 (24-BIT CONVERSIONS)
D31(MSB) D30 MSB 22 D15 D14 7 6 D29 21 D13 5 D28 20 D12 4 D27 19 D11 3 D26 18 D10 2 D25 17 D9 1 D24 16 D8 LSB D23 15 D7 0 D22 14 D6 0 D21 13 D5 0 D20 12 D4 0 D19 11 D3 0 D18 10 D2 OF D17 9 D1 CI1 D16 8 D0 CI0
Conversion Data Bits [31:16 for CS5531/33; 31:8 for CS5532/34]
These bits depict the latest output conversion.
NU (Not Used) [15:3 for CS5531/33; 7:3 for CS5532/34]
These bits are masked logic zero.
OF (Over-range Flag Bit) [2]
0 1 Bit is clear when over-range condition has not occurred (read only). Bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full scale (bipolar mode).
CI (Channel Indicator Bits) [1:0]
These bits indicate which physical input channel was converted. 00 01 10 11 Physical Channel 1 Physical Channel 2 Physical Channel 3 Physical Channel 4
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2.6.2. Output Coding
CS5531/33 16-Bit Output Coding Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Offset Binary FFFF FFFF -----FFFE 8000 -----7FFF 0001 -----0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFF 7FFF -----7FFE 0000 -----FFFF 8001 -----8000 8000 CS5532/34 24-Bit Output Coding Unipolar Input Voltage VFS-1.5 LSB Offset Binary FFFFFF -----FFFFFE 800000 -----7FFFFF 000001 -----000000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFFFF 7FFFFF -----7FFFFE 000000 -----FFFFFF 800001 -----800000 800000
>(VFS-1.5 LSB) FFFFFF
VFS/2-0.5 LSB
VFS/2-0.5 LSB
-0.5 LSB
-0.5 LSB
+0.5 LSB
+0.5 LSB
-VFS+0.5 LSB <(-VFS+0.5 LSB)
-VFS+0.5 LSB
<(+0.5 LSB)
<(+0.5 LSB)
000000 <(-VFS+0.5 LSB)
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 2. Output Coding for 16-bit CS5531/33 and 24-bit CS5532/34.
2.7. Digital Filter
The CS5531/32/33/34 have linear phase digital filters which are programmed to achieve a range of output word rates (OWRs) as stated in the ChannelSetup Register Descriptions section. The ADCs use a Sinc5 digital filter to output word rates at 3840 Hz (MCLK = 4.9152 MHz). Other output word rates are achieved by using a Sinc3 filter with a programmable decimation (see Figure 15). The Sinc3 is active for all output word rates except for the 3840 Hz (MCLK = 4.9152 MHz) rate. The converter's digital filters scale with MCLK. For example, with an output word rate of 120 Hz, the filter's corner frequency is typically 31 Hz. If MCLK is increased to 5.0 MHz, the OWR increases by 1.0175 percent and the filter's corner frequency moves to 31.54 Hz. Note that the converter isn't specified to run at MCLK clock frequencies greater than 5 MHz.
Gain (dB)
0 -40 -80
-120 0 60 120 180 240 300
Frequency (Hz)
Figure 15. Digital Filter Response (Word Rate = 60 Hz).
Frequency (Hz) 50 (MCLK = 4.096MHz) 60 (MCLK = 4.9152MHz)
Notch Depth (dB) TBD TBD
Frequency (Hz) TBD TBD
Minimum Attenuation (dB) TBD TBD
Table 3. Filter Notch Attenuation.
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2.8. Clock Generator
The CS5531/32/33/34 include an on-chip inverting amplifier which can be connected with an external crystal to provide the master clock for the chip. The chips are designed to operate using a 4.9152 MHz crystal; however, other crystal with frequencies between 1 MHz to 5 MHz can be used. One lead of the crystal should be connected to OSC1 and the other to OSC2. Lead lengths should be minimized to reduce stray capacitance. Note that while using the on chip oscillator, neither OSC1 or OSC2 is capable of directly driving any off chip logic. When the on chip oscillator is used, the voltage on OSC2 is typically 1/2 V peak-to-peak. This signal is not compatible with external logic unless additional external circuitry is added. The OSC2 output should be used if the crystal output is used to drive other logic. The designer can use an external CMOS compatible oscillator to drive OSC2 with a 1 MHz to 5 MHz clock for the ADC. In this scheme, OSC1 is left unconnected.
2.9. Power Supply Arrangements
The CS5531/32/33/34 are designed to operate from single or dual analog supplies and a single digital supply. The following power supply connections are possible: VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V VA+ = +3 V; VA- = -3 V; VD+ = +3 V Figure 16 illustrates the CS5532 connected with a single +5.0 V supply to measure differential inputs relative to a common mode of 2.5 V. Figure 17 illustrates the CS5532 connected with 2.5 V bipolar analog supplies and a +3 V to +5 V digital supply to measure ground referenced bipolar signals. Figure 18 illustrates the CS5532 connected with 3 V analog supplies and a +3 V digital supply to measure ground referenced bipolar signals. Figure 19 illustrates alternate bridge configurations which can be measured with the converter. Voltage V1 can be measured with the PGIA gain set to 1x as the input amplifier on this gain setting can go rail-to-rail. Voltage V2 should be measured with the PGIA gain set at 2x or higher as the instrumentation amplifier used on these gain ranges achieves lower noise.
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+5 V Analog Supply
10
0.1 F 5 VA+ 18 VREF+ 17 VREF3 C1 15 VD+ OSC2 9 10
0.1 F
Optional Clock Source 4.9152 MHz
OSC1
-
+
22 nF CS5532 4 1 2 20 19 7 8 C2 AIN1+ AIN1AIN2+ AIN2A0 A1 VA 6 CS SDI SDO SCLK DGND 16 14 13 12 11
Serial Data Interface
Figure 16. CS5532 Configured with a Single +5 V Supply.
+2.5 V Analog Supply
0.1 F 5 VA+ 18 VREF+ 17 VREF3 C1 15 VD+ OSC2 9
+3 V ~ +5 V Digital 0.1 F Supply Optional Clock Source 4.9152 MHz
OSC1
10
-
+
22 nF CS5532 4 1 2 20 19 7 8 C2 AIN1+ AIN1AIN2+ AIN2A0 A1 VA 6 CS SDI SDO SCLK DGND 16 14 13 12 11
Serial Data Interface
-2.5 V Analog Supply
Figure 17. CS5532 Configured with 2.5 V Analog Supplies.
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+3 V Analog Supply
10
0.1 F 5 VA+ 18 VREF+ 17 VREF3 C1 15 VD+ OSC2 9
0.1 F
OSC1
10
Optional Clock Source 4.9152 MHz
-
+
22 nF CS5532 4 1 2 20 19 7 8 C2 AIN1+ AIN1AIN2+ AIN2A0 A1 VA 6 CS SDI SDO SCLK DGND 16 14 13 12 11
Serial Data Interface
-3 V Analog Supply
Figure 18. CS5532 Configured with 3 V Analog Supplies.
V+
V+
V1
V2
V2
V1
(a)
(b)
Figure 19. Bridge with Series Resistors.
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2.10. Getting Started
This part has several features. From a software programmer's prospective, what should be done first? To begin, a 4.9152 MHz or 4.096 MHz crystal takes approximately 20 ms to start. To accommodate for this, it is recommended that a software delay of approximately 20 ms start the processor's ADC initialization code. Next, since the CS5531/32/33/34 do not provide a power-on-reset function, the user must first initialize the ADC to a known state. This is accomplished by resetting the ADC's serial port with the Serial Port Initialization sequence. This sequence resets the serial port to the command mode and is accomplished by transmitting 15 SYNC1 command bytes (0xFF hexadecimal), followed by one SYNC0 command (0xFE hexadecimal). Once the ADC is in a known state (in this case the command mode), the user must reset all the internal logic by performing a system reset. This is accomplished by setting the Reset System (RS) bit in the configuration register. After a system reset cycle is complete, the RS bit is automatically returned to logic 0, all on-chip logic is initialized to its proper state, and the ADC is returned to the command mode where it waits for the next valid command to execute. The next action is to initialize the voltage reference mode. The voltage reference select (VRS) bit in the configuration register must be set based upon the magnitude of the reference voltage between the VREF+ and the VREF- pins. After this, initialize the channel-setup registers (CSRs) as these registers determine how calibrations and conversions will be performed. Once the CSRs are initialized, the user has three options in calibrating the ADC: 1) don't calibrate and use the default settings; 2) perform self or system calibrations; or 3) upload previously saved calibration results to the offset and gain registers. Once calibrated, the ADC is ready to perform conversions.
2.11. PCB Layout
The CS5531/32/33/34 should be placed entirely over an analog ground plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
Note: See the CDB5531/32/33/34 data sheet for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.
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3. PIN DESCRIPTIONS
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK
AIN1+
AIN1C1
1 2
20 19
AIN2+
AIN2VREF+
DIFFERENTIAL ANALOG INPUT
CS5531/2
3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11
DIFFERENTIAL ANALOG INPUT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIGITAL GROUND POSITIVE DIGITAL POWER CHIP SELECT SERIAL DATA INPUT SERIAL DATA OUT SERIAL CLOCK INPUT
C2
VA+ VAA0 A1 OSC2 OSC1
VREFDGND VD+ CS SDI SDO SCLK
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK
AIN1+ AIN1-
1 2
24 23
AIN2+ AIN2AIN3+ AIN3-
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
VOLTAGE REFERENCE INPUT
AIN4+
AIN4C1
CS5533/4
3 4 5 6 7 8 9 10 11 12 22 21 20 19 18 17 16 15 14 13
VREF+
VREFDGND
C2
VA+ VAA0 A1 OSC2 OSC1
VOLTAGE REFERENCE INPUT DIGITAL GROUND POSITIVE DIGITAL POWER CHIP SELECT SERIAL DATA INPUT SERIAL DATA OUT SERIAL CLOCK INPUT
VD+
CS SDI
SDO SCLK
Clock Generator OSC1; OSC2 - Master Clock. An inverting amplifier inside the chip is connected between these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock for the device. Control Pins and Serial Data I/O CS - Chip Select. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK = 0.
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SDI - Serial Data Input. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input. A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0 - Logic Output (Analog)/Guard, A1 - Logic Output (Analog). The logic states of A0-A1 mimic the states of the D22/D10-D23/D11 bits of the channel-setup register. Logic Output 0 = VA-, and Logic Output 1 = VA+. A0 can be used as a guard drive for the instrumentation amplifier with proper setting of the GB bit in the Configuration Register. Measurement and Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input. Differential input pins into the CS5531. VREF+, VREF- - Voltage Reference Input. Fully differential inputs which establish the voltage reference for the on-chip modulator. C1, C2 - Amplifier Capacitor Inputs. Connections for the instrumentation amplifier's capacitor. Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. VD+ - Positive Digital Power. Positive digital supply voltage (nominally +3.0 V or +5 V). VA- - Negative Analog Power. Negative analog supply voltage. DGND - Digital Ground. Digital Ground.
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4. SPECIFICATION DEFINITIONS
Linearity Error The deviation of a code from a straight line which connects the two endpoints of the ADC transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of fullscale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs.
5. ORDERING GUIDE
Model Number CS5531-AS CS5533-AS CS5532-AS CS5532-BS CS5534-AS CS5534-BS Bits 16 16 24 24 24 24 Channels Linearity Error (Max) Temperature Range 2 4 2 2 4 4 0.003% 0.003% 0.003% 0.0015% 0.003% 0.0015% -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package 20-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP
DS289PP3
43
CS5531/32/33/34
6. PACKAGE DRAWINGS
20 PIN SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0 MAX 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040 8
MILLIMETERS MIN MAX -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03 0 8
NOTE
2,3 1 1
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
44
DS289PP3
CS5531/32/33/34
24 PIN SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.024 0.025 0 MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.027 0.040 8
MILLIMETERS MIN MAX -2.13 0.05 0.25 1.62 1.88 0.22 0.38 7.90 8.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03 0 8
NOTE
2,3 1 1
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS289PP3
45

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